Paper
24 October 2000 Analysis of fault coverage and simulation of test data compactors for online testing control units
Serge N. Demidenko
Author Affiliations +
Proceedings Volume 4228, Design, Modeling, and Simulation in Microelectronics; (2000) https://doi.org/10.1117/12.405404
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
This paper is related to synthesis of concurrently self- testing control units providing pre-defined level of fault coverage. Compaction of test data is one of the core elements of on-line monitoring over control flow execution in terms of its integrity and correctness. Traditionally, the most widely employed compression algorithm is so-called Signature Compression. It is based on the well-established theory on cyclic coding. Cyclic coding and related error correction are very efficient tools when errors lead to inversion of some bits in the initial bit sequence. However, error types and corresponding fault models in case of control unit monitoring are different. Two new fault models for control unit test data are introduced in the paper - shortening and lengthening of the bit sequence being compressed. Results of simulation and comparison of several compression algorithms for these fault models are presented in the paper. The control units of micro-programmed type are considered through out the paper though the results can be applicable to other control unit architectures.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Serge N. Demidenko "Analysis of fault coverage and simulation of test data compactors for online testing control units", Proc. SPIE 4228, Design, Modeling, and Simulation in Microelectronics, (24 October 2000); https://doi.org/10.1117/12.405404
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KEYWORDS
Transition metals

Computer simulations

Control systems

Data modeling

Diagnostics

Error analysis

Reliability

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