The first cost effective solution, to achieve a 100 nm gate with a 300 nm pitch, for ASICS manufacturing, is to validate a 193 nm technology using binary masks and weak OPC. This allows us to have zero defects mask with a relative short cycle time. In order to determine and minimize the CD dispersion resulting from the mask making process for ArF lithography, the following sources of errors have been studied: (1) Mask CD dispersion: the effect of CD dispersion was analyzed for different mask making processes (combinations of raster optical, raster e-beam and shape beam writers and dry and wet etch). Shape beam in combination with dry etch showed the best results in this study. CD dispersion at 1x of 3 nm is observed. (2) MEEF: the MEEF was determined using different methods and found to be 1.6 for a 300 nm pitch at 193 nm and NA equals 0.63/sigma equals 0.8. This value can be further improved when using quadrupole illumination or a higher NA. (3) Linearity and proximity effects on mask: the shape beam process shows better linearity and less proximity effects as compared to a raster tool based process. Without OPC correction, this difference is very important. The choice of the writing tool is less important with respect to proximity and linearity effects when using a model based OPC approach, since the effects are more or less systematic and can be compensated for. (4) Effect of quartz transmission at 193 nm: transmission variation at 193 nm of standard 248 nm quartz blanks is around three times higher than at 248 nm. This leads to a 3 nm CD variation, which is not negligible considering the 20 nm budget. A new type of blank is required. To achieve a 100 nm gate printing capability for low volume ASIC production a good understanding and control of all the steps in the mask process are needed. Furthermore, even if all these steps are well controlled, the total mask CD budget is still larger today than the budget indicated by the ITRS roadmap; 35% versus 30%.