You have requested a machine translation of selected content from our databases. This functionality is provided solely for your convenience and is in no way intended to replace human translation. Neither SPIE nor the owners and publishers of the content make, and they explicitly disclaim, any express or implied representations or warranties of any kind, including, without limitation, representations and warranties as to the functionality of the translation feature or the accuracy or completeness of the translations.
Translations are not retained in our system. Your use of this feature and the translations is subject to all use restrictions contained in the Terms and Conditions of Use of the SPIE website.
26 April 2001Some lithographic limits of back end lithography
At present we are now approaching the 130 nm technology node, one that a few short years ago we were forecasting would be the end of optical lithography. However, although we are now at this node, we have to use many Resolution Enhancement Techniques to print the desired features. These techniques can provide us with processes that are manufacturable but some of the side effects are not tolerable. This paper will show how the use of off-axis illumination can provide solutions for dense patterning in advanced interconnect. We will also show how the very same techniques that provide the solutions for dense features, can cause problems for more isolated features. The work will show that we can not longer select one technique to provide a solution for advanced features. The work will show that we can no longer select one technique to provide a solution for advanced patterning, but instead have to consider the patterning as an imaging system with several components. The differences in pattern fidelity between features of different density may be what leads us to utilize non- optical lithography.
The alert did not successfully save. Please try again later.
Martin McCallum, "Some lithographic limits of back end lithography," Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); https://doi.org/10.1117/12.425217