Coplanar waveguides on SOI and OPS substrates

Harold S. Gamble; Kam On Leong; Syed H. Raza; Brian Mervyn Armstrong; S. J. Neil Mitchell; Suidong Yang; Vince Fusco; Carson Stewart

doi:10.1117/12.425323

30 April 2001 Coplanar waveguides on SOI and OPS substrates

Harold S. Gamble, Kam On Leong, Syed H. Raza, Brian Mervyn Armstrong, S. J. Neil Mitchell, Suidong Yang, Vince Fusco, Carson Stewart

Author Affiliations +

Proceedings Volume 4407, MEMS Design, Fabrication, Characterization, and Packaging; (2001) https://doi.org/10.1117/12.425323
Event: Microelectronic and MEMS Technologies, 2001, Edinburgh, United Kingdom

Abstract

Silicon is being investigated as a low cost, low loss substrate for MMICs. The conflicting requirements of low resistivity silicon for active device fabrication and very high resistivity silicon for low microwave transmission losses have been met by two differing technologies. In one technology the low loss CPW lines are fabricated on oxidized porous silicon (OPS) formed on 1-3 (Omega) -cm (100) silicon substrates. In the other technology SOI substrates are produced by bonding 1-3 (Omega) -cm silicon wafers to 2-4 k(Omega) -cm handle wafers which are covered with a layer of silicon dioxide on a layer of polycrystalline silicon. To minimize bowing of the silicon substrate it was found necessary to limit the OPS thickness to 10 micrometers . For the CPW lines the microwave losses on the OPS substrates were 8.5 dB/cm at 30 GHz and on the SOI wafers they were 2.2 dB/cm. The SOI wafers offer considerable promise for reliable low cost low loss MMIC substrates.

Citation Download Citation

Harold S. Gamble, Kam On Leong, Syed H. Raza, Brian Mervyn Armstrong, S. J. Neil Mitchell, Suidong Yang, Vince Fusco, and Carson Stewart "Coplanar waveguides on SOI and OPS substrates", Proc. SPIE 4407, MEMS Design, Fabrication, Characterization, and Packaging, (30 April 2001); https://doi.org/10.1117/12.425323

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