Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways

Marnik Brunfaut; Wim Meeus; Jan M. Van Campenhout; Richard Annen; Patrick Zenklusen; Hans M. Melchior; Ronny Bockstaele; Luc Vanwassenhove; Jonathan L. Hall; Bjorn Wittman; Andreas Neyer; Paul L. Heremans; Jan Van Koetsem; Roger King; Hugo Thienpont; Roel G. Baets

doi:10.1117/12.450437

13 December 2001 Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways

Marnik Brunfaut, Wim Meeus, Jan M. Van Campenhout, Richard Annen, Patrick Zenklusen, Hans M. Melchior, Ronny Bockstaele, Luc Vanwassenhove, Jonathan L. Hall, Bjorn Wittman, Andreas Neyer, Paul L. Heremans, Jan Van Koetsem, Roger King, Hugo Thienpont, Roel G. Baets

Author Affiliations +

Proceedings Volume 4455, Micro- and Nano-optics for Optical Interconnection and Information Processing; (2001) https://doi.org/10.1117/12.450437
Event: International Symposium on Optical Science and Technology, 2001, San Diego, CA, United States

Abstract

Architectural studies have identified field-programmable gate arrays (FPGA) as a class of general-purpose very large scale integration components that could benefit from the introduction at the logic level of state-of-the-art massively parallel optical inter-chip interconnections. In this paper, we present a small-scale optoelectronic multi-FPGA demonstrator in which three optoelectronic enhanced FPGAs are interconnected by 2D Plastic Optical Fiber (POF) ribbon arrays. The full-custom FPGA chips consisting of an 8 X 8 array of very simple programmable logic cells are equipped with two optical sources and two receivers per FPGA cell yielding a maximum of 256 optical links per chip. The optical links are designed for signaling rates of 80 to 100 Mbit/s (160 to 200 Mbaud using Manchester coded data) compatible with the maximum clock frequency of the, in 0.6 micrometers CMOS implemented, FPGA chips. The results of parallel link experiments between such modules with both VCSELs and LEDs as sources will be shown. A large scale parallel bit error rate experiment at 90 Mbit/s/channel between two half-populated VCSEL-based FPGA modules with 112 of their 128 channels operational at bit error rates below 10^-13 on all active channels (approximately equals 10 Gbit/s/chip) proves the feasibility of this approach. We first briefly discuss the general architecture and the realization of the optoelectronic FPGA demonstrator system. We then present measurement results on the available modules, followed by some conclusions on this work.

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Marnik Brunfaut, Wim Meeus, Jan M. Van Campenhout, Richard Annen, Patrick Zenklusen, Hans M. Melchior, Ronny Bockstaele, Luc Vanwassenhove, Jonathan L. Hall, Bjorn Wittman, Andreas Neyer, Paul L. Heremans, Jan Van Koetsem, Roger King, Hugo Thienpont, and Roel G. Baets "Demonstrating optoelectronic interconnect in a FPGA-based prototype system using flip-chip mounted 2D arrays of optical components and 2D POF-ribbon arrays as optical pathways", Proc. SPIE 4455, Micro- and Nano-optics for Optical Interconnection and Information Processing, (13 December 2001); https://doi.org/10.1117/12.450437

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