Network processor architecture for flexible buffer management in very high speed line interfaces

Shimonishi Hideyuki; Murase Tutomu

doi:10.1117/12.434375

24 July 2001 Network processor architecture for flexible buffer management in very high speed line interfaces

Shimonishi Hideyuki, Murase Tutomu

Proceedings Volume 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III; (2001) https://doi.org/10.1117/12.434375
Event: ITCom 2001: International Symposium on the Convergence of IT and Communications, 2001, Denver, CO, United States

Abstract

In this paper, the proposed architecture is described and the results obtained when evaluating it in a typical application program for traffic handling are reported. It is shown that the architecture enables Weighted Round Robin packet scheduling at 4.1 Gbps line speed, in addition to 10 Gbps IP packet forwarding and 2.4 Gbps IP/ATM multi-layer switching.

Citation Download Citation

Shimonishi Hideyuki and Murase Tutomu "Network processor architecture for flexible buffer management in very high speed line interfaces", Proc. SPIE 4525, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, (24 July 2001); https://doi.org/10.1117/12.434375

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