Design of a parallel RISC image processor based on PCI bus

Xianyang Jiang; Xubang Shen; Tianxu Zhang

doi:10.1117/12.441675

20 September 2001 Design of a parallel RISC image processor based on PCI bus

Xianyang Jiang, Xubang Shen, Tianxu Zhang

Proceedings Volume 4555, Neural Network and Distributed Processing; (2001) https://doi.org/10.1117/12.441675
Event: Multispectral Image Processing and Pattern Recognition, 2001, Wuhan, China

Abstract

Low-level image processing operations usually involve simple and repetitive operations over the entire input images, thus image processor may communicate with the memory system or each other frequently, hence the image processor would provide high throughput rate. In this article we present an architectural design and analysis of a parallel RISC image processor. The processor was based on PCI bus to speed up a range of image processing operations. The other characteristic of the processor is that a new three-port hostbridge is integrated into the processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed.

Citation Download Citation

Xianyang Jiang, Xubang Shen, and Tianxu Zhang "Design of a parallel RISC image processor based on PCI bus", Proc. SPIE 4555, Neural Network and Distributed Processing, (20 September 2001); https://doi.org/10.1117/12.441675

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