Paper
11 March 2002 Robust and fast OPC approach for metal interconnects of 0.13um logic devices
Ji-Soong Park, Dong-Hyun Kim, Chul-Hong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyun-Woo Kim, Sun-Il Yoo
Author Affiliations +
Abstract
Insufficient metal overlaps over contacts and/or vias impact serious yield loss especially in the borderless-contact- style random logic devices. Vias which are not fully covered by interconnects cause not only the functional error due to the high via resistance but also the reliability problem such as electro migration. It is not sufficient to compensate only optical proximity effects such as line-end shortening and corner rounding for the overlap margin. Since mis-alignment between interconnects and over/underlying features is not negligible even using an advanced alignment system of step and scanner. Therefore, the need for aggressive OPC is increased to cope with the proximity effect and overlay error in metal interconnects. The proposed OPC approach gives a robust metal overlap with fast runtime and allowable data complexity by selective correction for the improperly overlapped contacts and vias. Experimental results for the test design show that the correction time of the metal interconnects takes 11 hours at HP5600 system by applying the proposed correction algorithm.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ji-Soong Park, Dong-Hyun Kim, Chul-Hong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyun-Woo Kim, and Sun-Il Yoo "Robust and fast OPC approach for metal interconnects of 0.13um logic devices", Proc. SPIE 4562, 21st Annual BACUS Symposium on Photomask Technology, (11 March 2002); https://doi.org/10.1117/12.458275
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Cited by 3 scholarly publications.
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KEYWORDS
Optical proximity correction

Metals

Logic devices

Optical alignment

Photomasks

Bridges

Resistance

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