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21 November 2001 Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders
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Abstract
The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.
© (2001) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter Celinski, Jose Fco. Lopez, Said F. Al-Sarawi, and Derek Abbott "Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders", Proc. SPIE 4591, Electronics and Structures for MEMS II, (21 November 2001); https://doi.org/10.1117/12.449155
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