Low-frequency process for silicon-on-insulator deep reactive ion etching

Matthew Wasilik; Albert P. Pisano

doi:10.1117/12.449003

21 November 2001 Low-frequency process for silicon-on-insulator deep reactive ion etching

Matthew Wasilik, Albert P. Pisano

Proceedings Volume 4592, Device and Process Technologies for MEMS and Microelectronics II; (2001) https://doi.org/10.1117/12.449003
Event: International Symposium on Microelectronics and MEMS, 2001, Adelaide, Australia

Abstract

Due to the inherently non-uniform etching effects in the standard DRIE (Deep Reactive Ion Etch) process, a new technique has been developed specifically for SOI (silicon on insulator) etching. The new system embodies a separate LF power supply that is pulsed when being applied to the platen during the etch cycle. This lends itself to assisting in the reduction of ionic charging at the insulator layer in deep trenches. Consequently, notching or footing of Si structures is disallowed. From this a decrease in over etch sensitivity emerges, with the end result being the ability to produce high-quality, large aspect ratio structures. Si etch rates in the same DRIE process may differ due to three basic effects: Aspect ratio dependent etch (ARDE), microloading (RIE-lag), and the general loading effect by which edges of the substrate etch faster than the center. When etching to a buried insulating layer these effects tend to indirectly encourage footing. The purpose of the research involved was to find optimal process parameters that would minimize footing. Factorial design of experiment technique was used to accomplish this in a two step process. First, main and second order effects on etch-rate uniformity were studied. Then, once supplied with process parameters that minimize uniformity effects, parameter settings that minimize footing were found. The end result is a purse of optimized DRIE-SOI recipes that produce superb high-aspect ratio Silicon structures.

Citation Download Citation

Matthew Wasilik and Albert P. Pisano "Low-frequency process for silicon-on-insulator deep reactive ion etching", Proc. SPIE 4592, Device and Process Technologies for MEMS and Microelectronics II, (21 November 2001); https://doi.org/10.1117/12.449003

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