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1 July 2002 Shaped e-beam lithography integration work for advanced ASIC manufacturing: progress report
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Abstract
For the sub-90 nm node integrated circuits design rules, ITRS forecasts require minimal gate line width down to 55-35 nm. To reach such aggressive targets, most advanced optical lithography tools combined with all reticle enhancement techniques will be requested inducing important manufacturing cost and mask cycle time increase. In order to address prototyping market and reduce fabrication cost, shaped electron beam lithography may represent a technological alternative for cost reduction due to its high resolution and potential throughput capabilities. This paper is focused on the integration of this technology in standard ASIC plant, including resist process and overlay capabilities.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Laurent Pain, Murielle Charpin, Yves LaPlanche, and Daniel Henry "Shaped e-beam lithography integration work for advanced ASIC manufacturing: progress report", Proc. SPIE 4688, Emerging Lithographic Technologies VI, (1 July 2002); https://doi.org/10.1117/12.472335
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