Quantification of OPC performance of 150-nm gates using top-down CD-SEM

Ashesh Parikh; Haiqing Zhou; Chih-Yu Wang; Craig W. MacNaughton

doi:10.1117/12.473489

16 July 2002 Quantification of OPC performance of 150-nm gates using top-down CD-SEM

Ashesh Parikh, Haiqing Zhou, Chih-Yu Wang, Craig W. MacNaughton

Proceedings Volume 4689, Metrology, Inspection, and Process Control for Microlithography XVI; (2002) https://doi.org/10.1117/12.473489
Event: SPIE's 27th Annual International Symposium on Microlithography, 2002, Santa Clara, California, United States

Abstract

Optical proximity correction using both model-based and selective size adjust techniques was used as means to correct the distortion of patterns in silicon from drawn data. The performance of these corrections on silicon was evaluated using top-down SEM for both active area and gate wafers post-pattern and post-etch steps. Figure of merit such as corner rounding radius and line-edge roughness were measured. By overlapping the drawn data to the processed image, metric such as overlapping area and critical shape difference were extracted. This resulted in a range of metrics that quantified the performance of the proximity correction that was applied on the mask with reference to drawn data.

Citation Download Citation

Ashesh Parikh, Haiqing Zhou, Chih-Yu Wang, and Craig W. MacNaughton "Quantification of OPC performance of 150-nm gates using top-down CD-SEM", Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); https://doi.org/10.1117/12.473489

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