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12 July 2002 Crossing the divide between lithography and chip design
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0.7X reduction every two years, as required by Moore's Law, has increased the emphasis on low k1 imaging. Low k1 is a way to extend each wavelength one node. However, with low k1 imaging, a significant divide opens between the desires of the chip designer and the realities of lithographic reproduction. As k1 decreases from the safe and comfortable 0.8 value enjoyed in the 1980s, to the more stringent 0.5 adopted in production in the 90s, lithographers had to beg designers to let them do line biasing and place hammerheads at the ends of gates in order to compensate for simple proximity effects like iso-dense bias and line end shortening. Now, in the new millenium, many chip makers have to develop processes that work below 0.4 k1, which brings new tensions between the designer and the lithographer in the forms of design rule restrictions, 2D OPC, forbidden pitches, phase assignments, double exposure decompositions, etc.
© (2002) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
William H. Arnold, J. Fung Chen, and Kurt E. Wampler "Crossing the divide between lithography and chip design", Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002);

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