Novel scheme for a higher bandwidth sensor readout

Ashok Srivastava; Harish N. Venkata; Pratul K. Ajmera

doi:10.1117/12.475050

11 July 2002 Novel scheme for a higher bandwidth sensor readout

Ashok Srivastava, Harish N. Venkata, Pratul K. Ajmera

Proceedings Volume 4700, Smart Structures and Materials 2002: Smart Electronics, MEMS, and Nanotechnology; (2002) https://doi.org/10.1117/12.475050
Event: SPIE's 9th Annual International Symposium on Smart Structures and Materials, 2002, San Diego, California, United States

Abstract

Circuit design for a novel scheme for converting a multiple- valued output voltage forma sensor into a binary-coded output for signal processing is described here. Floating gate MOSFETs and floating gate potential diagrams have been used to design a readout integrated circuit in a standard 1.5 micrometers digital CMOS VLSI technology. The physical design is simulated and tested with SPICE using MOSIS BSIM3 MOS model parameters. Initial results on fabricated devices for the conversion of quaternary input into binary output have shown agreement with the corresponding simulated values. The method is simple and compatible with current CMOS processes. The circuit can be integrated with output of a sensor fabricated in MEMS-CMOS technology.

Citation Download Citation

Ashok Srivastava, Harish N. Venkata, and Pratul K. Ajmera "Novel scheme for a higher bandwidth sensor readout", Proc. SPIE 4700, Smart Structures and Materials 2002: Smart Electronics, MEMS, and Nanotechnology, (11 July 2002); https://doi.org/10.1117/12.475050

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