Investigating into mask contribution to device performance and chip functionality

Andrew J. Watts; Jed H. Rankin

doi:10.1117/12.476931

1 August 2002 Investigating into mask contribution to device performance and chip functionality

Andrew J. Watts, Jed H. Rankin

Author Affiliations +

Proceedings Volume 4754, Photomask and Next-Generation Lithography Mask Technology IX; (2002) https://doi.org/10.1117/12.476931
Event: Photomask and Next Generation Lithography Mask Technology IX, 2002, Yokohama, Japan

Abstract

Device performance and functionality can be impacted by many factors, both physical and electrical. Close interaction between the lithographer and mask maker is useful in the deconvolution of the mask contributions to device speed and functionality. Across plate image size variation, linearity, orientation and proximity effects (both local and global) influence the Across Chip Linewidth Variation (ACLV). ACLV, in turn, has a strong correlation to overall device performance. Several situations in which integrated circuit functionality and performance were correlated to mask systematics will be presented along with resolution of the described issues. Methodologies for separating the mask components from the wafer level process components will also be discussed. Mask specifications are often derived by simply scaling the previous technology, rather than basing the specifications on technical requirements. A methodology will be derived which links technological device specifications and the anticipated mask exposure conditions to the required mask specifications.

Citation Download Citation

Andrew J. Watts and Jed H. Rankin "Investigating into mask contribution to device performance and chip functionality", Proc. SPIE 4754, Photomask and Next-Generation Lithography Mask Technology IX, (1 August 2002); https://doi.org/10.1117/12.476931

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