Study of thread-level parallelism in a video encoding application for chip multiprocessor design

Eric Debes; Greg Kaine

doi:10.1117/12.452439

21 November 2002 Study of Thread Level Parallelism in a Video Encoding Application for Chip Multiprocessor Design

Eric Debes, Greg Kaine

Proceedings Volume 4790, Applications of Digital Image Processing XXV; (2002) https://doi.org/10.1117/12.452439
Event: International Symposium on Optical Science and Technology, 2002, Seattle, WA, United States

Abstract

In media applications there is a high level of available thread level parallelism (TLP). In this paper we study the intra TLP in a video encoder. We show that a well-distributed highly optimized encoder running on a symmetric multiprocessor (SMP) system can run 3.2 faster on a 4-way SMP machine than on a single processor. The multithreaded encoder running on an SMP system is then used to understand the requirements of a chip multiprocessor (CMP) architecture, which is one possible architectural direction to better exploit TLP. In the framework of this study, we use a software approach to evaluate the dataflow between processors for the video encoder running on an SMP system. An estimation of the dataflow is done with L2 cache miss event counters using Intel® VTune^TMperformance analyzer. The experimental measurements are compared to theoretical results.

Citation Download Citation

Eric Debes and Greg Kaine "Study of Thread Level Parallelism in a Video Encoding Application for Chip Multiprocessor Design", Proc. SPIE 4790, Applications of Digital Image Processing XXV, (21 November 2002); https://doi.org/10.1117/12.452439

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