Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET

Jae-hong Kim; Geun-ho Kim; Suk-woong Ko; Hak-kee Jung

doi:10.1117/12.469072

14 November 2002 Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET

Jae-hong Kim, Geun-ho Kim, Suk-woong Ko, Hak-kee Jung

Proceedings Volume 4935, Smart Structures, Devices, and Systems; (2002) https://doi.org/10.1117/12.469072
Event: SPIE's International Symposium on Smart Materials, Nano-, and Micro- Smart Systems, 2002, Melbourne, Australia

Abstract

In this paper, we have investigated double gate (DG) MOSFET structure, which has main gate (MG) and two side gates (SG). We know that optimum side gate voltage for each side gate length is about 2V in the main gate 50nm. Also, we know that optimum side gate length for each main gate length is 70nm above. DG MOSFET shows a small threshold voltage (V_th) roll-off. From the I-V characteristics, we obtained I_Dsat=510μA/μm at V_MG=V_DS=1.5V and V_SG=3.0V for DG MOSFET with the main gate length of 50nm and the side gate length of 70nm. The subthreshold slope is 86mV/decade, transconductance is 111μA/V and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Then, we have investigated the advantage of this structure for the application to multi-input NAND gate logic. Also, we have presented that TCAD simulator is suitable for device simulation.

Citation Download Citation

Jae-hong Kim, Geun-ho Kim, Suk-woong Ko, and Hak-kee Jung "Optimization of side gate length and side gate voltage for sub-100-nm double-gate MOSFET", Proc. SPIE 4935, Smart Structures, Devices, and Systems, (14 November 2002); https://doi.org/10.1117/12.469072

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