Challenges of image placement and overlay at the 90-nm and 65-nm nodes

Walter J. Trybula

doi:10.1117/12.485036

2 June 2003 Challenges of image placement and overlay at the 90-nm and 65-nm nodes

Walter J. Trybula

Proceedings Volume 5038, Metrology, Inspection, and Process Control for Microlithography XVII; (2003) https://doi.org/10.1117/12.485036
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

The technology acceleration of the ITRS Roadmap has many implications on both the semiconductor supplier community and the manufacturers. INTERNATIONAL SE-MATECH has been leading and supporting efforts to investigate the impact of the tech-nology introduction. This paper examines the issue of manufacturing tolerances available for image placement on adjacent critical levels (overlay) at the 90nm and 65nm technol-ogy nodes. The allowable values from the 2001 release of the ITRS Roadmap are 32nm for the 90nm node, and 23nm for the 65nm node. Even the 130nm node has overlay requirements of only 46nm. Employing tolerances that can be predicted, the impact of existing production/processing tolerance accumulation can provide an indication of the challenges facing the manufacturer in the production of 90nm and 65nm Node devices.

Citation Download Citation

Walter J. Trybula "Challenges of image placement and overlay at the 90-nm and 65-nm nodes", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); https://doi.org/10.1117/12.485036

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