Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures

Philippe Leray; David W. Laidler; Ivan K.A. Pollentier

doi:10.1117/12.482817

2 June 2003 Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures

Philippe Leray, David W. Laidler, Ivan K.A. Pollentier

Author Affiliations +

Proceedings Volume 5038, Metrology, Inspection, and Process Control for Microlithography XVII; (2003) https://doi.org/10.1117/12.482817
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

With each new technology node, the corresponding overlay requirements become tighter. It has been shown that differences can exist between the pattern placement error of the relatively large frame in frame type overlay structures typically used for overlay measurement and control and real device structures. These differences can become a significant part of the total overlay budget. It is therefore necessary to identify the magnitude of these differences and establish whether they can be corrected. In order to investigate these differences in pattern placement error, an alternative metrology technique needed to be established which was capable of measuring the overlay of real device structures. In the first part of this paper we show that CD SEM Overlay Metrology offers comparable precision to that of the more traditional measurement of large frame in frame type overlay structures on an optical overlay tool. In the second part of the paper we apply this metrology technique to evaluate the pattern placement errors across the field of a step and scan exposure tool for different illumination modes. This is then compared to that obtained using the more traditional optical overlay metrology technique. Finally we discuss how these differences can be handled in a production environment in order to obtain optimum overlay performance.

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Philippe Leray, David W. Laidler, and Ivan K.A. Pollentier "Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); https://doi.org/10.1117/12.482817

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KEYWORDS

Personal protective equipment

Overlay metrology

Semiconducting wafers

Metrology

Reticles

Scanning electron microscopy

Data modeling

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