Overlay metrology simulations: analytical and experimental validations

Joel L. Seligson; Boris Golovanevsky; Jorge M. Poplawski; Michael E. Adel; Richard M. Silver

doi:10.1117/12.483661

2 June 2003 Overlay metrology simulations: analytical and experimental validations

Joel L. Seligson, Boris Golovanevsky, Jorge M. Poplawski, Michael E. Adel, Richard M. Silver

Proceedings Volume 5038, Metrology, Inspection, and Process Control for Microlithography XVII; (2003) https://doi.org/10.1117/12.483661
Event: Microlithography 2003, 2003, Santa Clara, California, United States

Abstract

We have previously reported on an overlay metrology simulation platform, used for modeling both the effects of overlay metrology tool behavior and the impact of target design on the ultimate metrology performance. Since our last report, the simulation platform has been further enhanced, consisting now of eleven PCs and running commercial software both for lithography (PROLITH) and rigorous Maxwell calculations (EM-Suite). In this paper we report on the validation of the metrology simulations by comparing them to both analytical calculations and to experimental results. The analytical validation is based on the classical calculation of the diffraction of a polarized plane wave from a perfectly conducting half plane. For the experimental validation, we chose an etched silicon wafer manufactured by International SEMATECH (ISMT) and characterized at National Institute of Science and Technology (NIST). The advantages of this wafer are its well known topography and its suite of different metrology targets. A good fit to both analytical and experimental results is demonstrated, attesting to the capabilities of our enhanced simulation platform. The results for both the analytical and experimental validations are presented.

Citation Download Citation

Joel L. Seligson, Boris Golovanevsky, Jorge M. Poplawski, Michael E. Adel, and Richard M. Silver "Overlay metrology simulations: analytical and experimental validations", Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); https://doi.org/10.1117/12.483661

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