Layout optimization at the pinnacle of optical lithography

Lars W. Liebmann; Greg A. Northrop; James Culp; Leon Sigal; Arnold Barish; Carlos A. Fonseca

doi:10.1117/12.485245

10 July 2003 Layout optimization at the pinnacle of optical lithography

Lars W. Liebmann, Greg A. Northrop, James Culp, Leon Sigal, Arnold Barish, Carlos A. Fonseca

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.485245
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

This paper attempts to shed more light on the widely acknowledged need to improve the manufacturabilty of itnegrated chip layouts for sub-100nm technology nodes. After reviewing the parametric performance targets and tiem constaints of the 65nm and 45nm technology nodes, the paper elaborates on the principles of popular resolution enhancement techniques, their impact on chip layouts, and the opportunity for borad layout improvement which they afford. Finally, the viability and feasibility of layout optimization based on a design-for-manufacturability mantra and enabled through "radically design restrictions" is explored.

Citation Download Citation

Lars W. Liebmann, Greg A. Northrop, James Culp, Leon Sigal, Arnold Barish, and Carlos A. Fonseca "Layout optimization at the pinnacle of optical lithography", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.485245

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