Performance-impact limited-area fill synthesis

Yu Chen; Puneet Gupta; Andrew B. Kahng

doi:10.1117/12.487732

10 July 2003 Performance-impact limited-area fill synthesis

Yu Chen, Puneet Gupta, Andrew B. Kahng

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.487732
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manufacturability and performance predictability, area fill features are inserted into the layout to imrpove uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertion. We then give the first formulation of the Performance Impact Limited Fill (PIL-Fill) problem, and describe three practical solution approaches based on Integer Linear Programming (ILP-I and ILP-II) and the Greedy method. We test our methods on two layout test cases obtained from industry. Compared with the normal fill method, our ILP-II method achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact, while maintaining identical quality of the layout density control.

Citation Download Citation

Yu Chen, Puneet Gupta, and Andrew B. Kahng "Performance-impact limited-area fill synthesis", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.487732

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