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This paper reports the development of a low-cost 128 x 128 uncooled infrared focal plane array (FPA) based on suspended and thermally isolated CMOS p+-active/n-well diodes. The FPA is fabricated using a standard 0.35 μm CMOS process followed by simple post-CMOS bulk micromachining that does not require any critical lithography or complicated deposition steps; and therefore, the cost of the uncooled FPA is almost equal to the cost of the CMOS chip. The post-CMOS fabrication steps include an RIE etching to reach the bulk silicon and an anisotropic silicon etching to obtain thermally isolated pixels. During the RIE etching, CMOS metal layers are used as masking layers, and therefore, narrow openings such as 2 μm can be defined between the support arms. This approach allows achieving small pixel size of 40 μm x 40 μm with a fill factor of 44%. The FPA is scanned at 30 fps by monolithically integrated multi-channel parallel readout circuitry which is composed of low-noise differential transconductance amplifiers, switched capacitor (SC) integrators, sample-and-hold circuits, and various other circuit blocks for reducing the effects of variations in detector voltage and operating temperature. The fabricated detector has a temperature coefficient of -2 mV/K, a thermal conductance value of 1.8 x 10-7 W/K, and a thermal time constant value of 36 msec, providing a measured DC responsivity (R) of 4970 V/W under continuous bias. Measured detector noise is 0.69 μV in 8 kHz bandwidth at 30 fps scanning rate, resulting a measured detectivity (D*) of 9.7 x 108 cm√HzW. Contribution of the 1/f noise component is found to be negligible due to the single crystal nature of the silicon n-well and its low value at low bias levels. The noise of the readout circuit is measured as 0.76 μV, resulting in an expected NETD value of 1 K when scanned at 30 fps using f=1 optics. This NETD value can be decreased below 350 mK by decreasing the electrical bandwidth with the help of increased number of parallel readout channels and by optimizing the post-CMOS etching steps. The uniformity of the array is very good due to the mature CMOS fabrication technology. The measured uncorrected differential voltage non-uniformity for the 128 x 128 array pixels after the CMOS fabrication is 0.2% with a standard deviation of only 1.5 mV, which is low due to the improved array structure that can compensate for the voltage drops along the routing resistances in the array. Non-uniformity of temperature sensitivity of the array pixels is measured to be less than 3% with a mean and standard deviation of -2.05 mV/K and 61 μV/K, respectively. The temperature sensitivity of the differential pixel voltages has a measured mean value of 2.3 μV/K, relaxing the requirements on the temperature stabilization. Considering its performance and its simple fabrication steps, the proposed method is very cost-effective to fabricate large format focal plane arrays for low-cost infrared imaging applications.
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