0.25-µm technology arithmetic codec for mobile multimedia communicators

Alberto Alvarez; Sebastian Lopez; Jose Fco. Lopez; Roberto Sarmiento

doi:10.1117/12.499051

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21 April 2003 0.25-μm technology arithmetic codec for mobile multimedia communicators

Alberto Alvarez, Sebastian Lopez, Jose Fco. Lopez, Roberto Sarmiento

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Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.499051
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

Low power dissipation is a must when dealing with mobile devices due to the influence related to its weight and hence, its portability. In this paper, the implementation of a 0.25 mm technology arithmetic codec with a good power/area/performance trade-off is presented. One of the key aspects introduced in order to obtain good performance is the fact of using low precision arithmetic rather than full precision, allowing the elimination of multiplications and divisions needed in order to process symbols and coefficients. These operations are replaced by shift/add operations, minimizing the complexity of the algorithm and improving the encoding and decoding process. The chip has been described in a high level language, ensuring its portability to other technologies. The implementation gives as result a 25 mm² chip, pads included, with a total power dissipation of 300 mW and a frequency of operation of 10 MHz.

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Alberto Alvarez, Sebastian Lopez, Jose Fco. Lopez, and Roberto Sarmiento "0.25-μm technology arithmetic codec for mobile multimedia communicators", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.499051

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