New distributed arithmetic discrete wavelet packet transform architecture

Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Rafael Gadea; Ricardo Colom

doi:10.1117/12.499056

21 April 2003 New distributed arithmetic discrete wavelet packet transform architecture

Guillermo Paya, Marcos M. Peiro, J. Francisco Ballester, Rafael Gadea, Ricardo Colom

Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.499056
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain

Abstract

The present paper describes a new architecture for a Discrete Wavelet Packet Transform (DWPT) based on a folded Distributed Arithmetic (DA) implementation, which makes possible to expand two complete stages (4-subband DWPT). The proposed parameterized architecture can use different CDF wavelet coefficients with modified precision. As the distributed arithmetic technique brings the possibility to make scalable designs, the proposed architecture can be easily parameterized. The data input and coefficient precision can be increased modifying the register size and the space memory, respectively. The number of coefficients can be change too increasing the memory and replicating the register structure. Our architecture uses only two FIR filters (high-pass and low-pass) that are folded to calculate various wavelet stages together in time. A discrete DWPT implementation using CDF(9/7) wavelet coefficients are implemented on VIRTEX-E1000-6 FPGA for different precisions. Finally, the use of both, the folding technique and the DA structure has offered a frequency operation of 75 MHz with 393 Flip-flop Slices (with 8 bits precision operation) on the FPGA.

Citation Download Citation

Guillermo Paya, Marcos M. Peiro, J. Francisco Ballester, Rafael Gadea, and Ricardo Colom "New distributed arithmetic discrete wavelet packet transform architecture", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.499056

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