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Nowadays digital networks require architectures based on standards that are implemented independently of the technology. Besides, these network specifications can easily change to include novel services. For these reasons, dominant trends are to design and verify systems at high level, prior to technology mapping. In this paper, a methodology is proposed to obtain a full verified system from an architecture specification. In order to validate this methodology, a system specification document is used as starting point. This specified system is partitioned in average size modules and then each module is described itself in design specification documents, which are the basis of their implementation using Hardware Description Languages (HDL). Each module is verified based on test specification documents generated along with the design specification. Finally, all the modules are interconnected and verified using an automatic test vector generator. Firstly, this approach introduces a method that, independently of the size of the system, improves reliability in the results, and secondly, it documents all the steps performed during the different stages. In order to validate this methodology, SDH (Synchronous Digital Hierarchy) and ATM (Asynchronous Transfer Mode) standards was chosen. Based on these standards, an ATM over SDH transceiver with add/drop functionality is studied, designed, implemented and verified. This system is described and verified using HDL and, after that, it is synthesized in FPGA devices. The obtained results show that a complex digital system has been developed guaranteeing the specifications, and, on the other hand, the optimization of the human resources and the effort of engineering. This methodology encourages the documentation process while the system is developed, easing the knowledge transfer process.
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