Translator Disclaimer
Paper
21 April 2003 State of the art in CMOS threshold logic VLSI gate implementations and systems
Author Affiliations +
Proceedings Volume 5117, VLSI Circuits and Systems; (2003) https://doi.org/10.1117/12.497792
Event: Microtechnologies for the New Millennium 2003, 2003, Maspalomas, Gran Canaria, Canary Islands, Spain
Abstract
In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in CMOS. This paper presents a summary of the recent developments in TL circuit design. High-performance TL gate circuit implementations are compared, and a number of their applications in computer arithmetic operations are reviewed. It is shown that the application of TL in computer arithmetic circuit design can yield designs with significantly reduced transistor count and area while at the same time reducing circuit delay and power dissipation when compared to conventional CMOS logic.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter Celinski, Sorin D. Cotofana, Jose Fco. Lopez, Said F. Al-Sarawi, and Derek Abbott "State of the art in CMOS threshold logic VLSI gate implementations and systems", Proc. SPIE 5117, VLSI Circuits and Systems, (21 April 2003); https://doi.org/10.1117/12.497792
PROCEEDINGS
12 PAGES


SHARE
Advertisement
Advertisement
Back to Top