A pipeline memory-efficient programmable architecture for the 2D discrete wavelet transform using lifting scheme

Sara Bolouki; Omid Fatemi

doi:10.1117/12.503183

23 June 2003 A pipeline memory-efficient programmable architecture for the 2D discrete wavelet transform using lifting scheme

Sara Bolouki, Omid Fatemi

Author Affiliations +

Proceedings Volume 5150, Visual Communications and Image Processing 2003; (2003) https://doi.org/10.1117/12.503183
Event: Visual Communications and Image Processing 2003, 2003, Lugano, Switzerland

Abstract

In this paper we propose a dedicated architecture to implement a 2-D Discrete Wavelet Transform (DWT) by using the lifting scheme method. The advantages of lifting scheme are lower computational complexity, transforming signal without extension and reduced memory requirement. The proposed architecture is re-configurable for 5/3 and 9/7 filters and employs folded configuration to reduce the hardware cost and achieve higher hardware utilization. The architecture is useful for VLSI implementation and various image- video applications. The design has been modeled by VHDL language and simulated by Modelsim and it is fully synthesizable.

Citation Download Citation

Sara Bolouki and Omid Fatemi "A pipeline memory-efficient programmable architecture for the 2D discrete wavelet transform using lifting scheme", Proc. SPIE 5150, Visual Communications and Image Processing 2003, (23 June 2003); https://doi.org/10.1117/12.503183

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