Interconnect effects in deep submicron implementation of high performance arithmetic architectures

Pedram Mokrian; Graham A. Jullien; Majid Ahmadi

doi:10.1117/12.506651

24 December 2003 Interconnect effects in deep submicron implementation of high performance arithmetic architectures

Pedram Mokrian, Graham A. Jullien, Majid Ahmadi

Proceedings Volume 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII; (2003) https://doi.org/10.1117/12.506651
Event: Optical Science and Technology, SPIE's 48th Annual Meeting, 2003, San Diego, California, United States

Abstract

The conventional trend in algorithm implementation has been the reliance on advancements in process technology in order to satisfy the ever-increasing demand for high-speed processors, and computational systems. As current device technology approaches sub-100nm minimum device size, not only does the device geometry decrease, but switching times, and operating voltages also scale down. These gains come at the expense of increased layout complexity, and a greater susceptibility to parasitic effects in the interconnections. In this paper we will briefly overview the challenges that digital designers will have to face in the imminent future, and will provide suggestions on algorithmic measures which may be taken in order to overcome some of these obstacles. To illustrate our point, we will present an analysis of a digital multiplication algorithm, which is predicted to outperform current schemes, for future technologies.

Citation Download Citation

Pedram Mokrian, Graham A. Jullien, and Majid Ahmadi "Interconnect effects in deep submicron implementation of high performance arithmetic architectures", Proc. SPIE 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, (24 December 2003); https://doi.org/10.1117/12.506651

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