Analysis and potentialities of backside-illuminated thinned CMOS imagers

Cecilia Marques Vatus; Pierre Magnan

doi:10.1117/12.513893

19 February 2004 Analysis and potentialities of backside-illuminated thinned CMOS imagers

Cecilia Marques Vatus, Pierre Magnan

Proceedings Volume 5251, Detectors and Associated Signal Processing; (2004) https://doi.org/10.1117/12.513893
Event: Optical Systems Design, 2003, St. Etienne, France

Abstract

CMOS imagers, now considered as a valuable alternative to CCD in many application fields, have their quantum efficiency reduced by optical filtering effects due to complex top layers structure and limited fill factor. Thinning and backside illumination (BI) have been successfully applied to CCD image sensor to improve their quantum efficiency. It can potentially be similarly applied to CMOS imagers in an attempt to allow, both the increase of impinging photons number on the photosensitive area through the suppression of top layers stack filtering, and the use of a maximal fill factor value, the whole backside surface being photosensitive. But, it has to take into account the specific features of CMOS process, mostly the limited EPI thickness in the case of the heavily doped substrate option.

Citation Download Citation

Cecilia Marques Vatus and Pierre Magnan "Analysis and potentialities of backside-illuminated thinned CMOS imagers", Proc. SPIE 5251, Detectors and Associated Signal Processing, (19 February 2004); https://doi.org/10.1117/12.513893

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