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17 December 2003 Full-chip application for SRAM gate at 100-nm node and beyond using chromeless phase lithography
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High speed circuit usually requires additional gate scaling regardless of its developed technology node. In this paper, we demonstrate the full-chip-level wafer result for 100nm node SRAM gate and the possibility of future gate scaling. Test reticle is manufactured using chromeless phase lithography(CPL). CPL technology uses a COG that consists of p -phased-etched quartz and chrome shield for various gate CD formation. Critical transistor area is 100% transmission PSM. However, less-critical area should be a chrome for adequate CD control. Because light interference is weakened in phase area according to the separation of paired phase edges increase. The optical performance and manufacturing issues of CPL are evaluated compared to other PSM technologies. Finally, we describe how to optimize the CPL mask using simulation and wafer analysis to obtain the acceptable OCV and DOF margin for volume production.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ji-Soong Park, Sung-Hyuck Kim, In-Kyun Shin, Sung-Woon Choi, Jung-Min Sohn, Jae-Han Lee, Hye-soo Shin, Thomas L. Laidig, Douglas J. Van Den Broeke, and J. Fung Chen "Full-chip application for SRAM gate at 100-nm node and beyond using chromeless phase lithography", Proc. SPIE 5256, 23rd Annual BACUS Symposium on Photomask Technology, (17 December 2003);


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