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8 June 2004 High-speed lateral PIN photodiodes in silicon technologies
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High speed, efficient photodetectors are difficult to fabricate in standard silicon fabrication processes due to the long absorption length of silicon. However, high performance servers will soon require dense optical interconnects with low cost and high reliability, and this trend favors monolithic silicon receivers over hybrid counterparts. Recently, lateral PIN photodiode structures have been demonstrated in silicon CMOS technology with little or no process modifications. Optical receivers based on these detectors have achieved record performance in terms of speed and sensitivity. This paper will discuss the advantages, issues and recent advances in silicon-based photodetectors and optical receivers. This includes the fastest photodetector ever implemented in a standard bulk CMOS process, a 13.9 Gb/s lateral trench detector implemented in a modified EDRAM process, and a >15 GHz pure germanium photodiode grown directly on a silicon substrate.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jeremy D. Schaub, Steven J. Koester, Gabriel Dehlinger, Q. Christine Ouyang, Drew Guckenberger, Min Yang, Dennis L. Rogers, Jack Chu, and Alfred Grill "High-speed lateral PIN photodiodes in silicon technologies", Proc. SPIE 5353, Semiconductor Photodetectors, (8 June 2004);

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