Submicron MOSFET Fabrication With X-Ray Lithography

R. P. Jaeger; M. Karnezos; H. Nakano

doi:10.1117/12.947488

20 June 1985 Submicron MOSFET Fabrication With X-Ray Lithography

R. P. Jaeger, M. Karnezos, H. Nakano

Proceedings Volume 0537, Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV; (1985) https://doi.org/10.1117/12.947488
Event: 1985 Microlithography Conferences, 1985, Santa Clara, United States

Abstract

X-ray lithography has been applied in a single-layer resist process to fabricate n-channel enhancement field-effect transistors with effective channel lengths (L_eff) and channel widths (We_ff) as small as small as 0.9 Lim and 0.5 Lim, respectively. The yields on 3" wafers ranged from as high as 50 % for the smallest MOSFETs with L_eff/W_eff of 0.9/0.5 to above 90% for those with Leff/Weff of 2.2/0.5 and 0.9/1.7 without process optimization. This report outlines the mask technology and the device fabrication process. The MOSFET performance is discussed with emphasis on threshold voltage and subthreshold slope uniformity and on wafer-to-wafer variations.

Citation Download Citation

R. P. Jaeger, M. Karnezos, and H. Nakano "Submicron MOSFET Fabrication With X-Ray Lithography", Proc. SPIE 0537, Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV, (20 June 1985); https://doi.org/10.1117/12.947488

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