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24 May 2004 A comparison of methods for in-chip overlay control at the 65-nm node
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Abstract
Overlay metrology for production line-monitor and advanced process control (APC) has been dominated by 4-corner box-in-box (BiB) methods for many years. As we proceed following the ITRS roadmap with the development of 65 nm technologies and beyond, it becomes apparent that current overlay methodologies are becoming inadequate for the stringent requirements that lie ahead. It is already apparent that kerf metrology of large scale BiB structures does not correlate well with in-chip design-rule features. The recent introduction of the Advanced Imaging Metrology (AIM) target, utilizing increased information content and advanced design and process compatibility, has demonstrated significant improvements in precision and overlay mark fidelity (OMF) in advanced processes. This paper compares methodologies and strategies for addressing cross-field variation of overlay and pattern placement issues. We compare the trade-offs of run-time intra-field sampling plans and the use of off-line lithography characterization and advanced modeling analysis, and propose new methodologies to address advanced overlay metrology and control.
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John C. Robinson, Mark Stakely, Jorge M. Poplawski, Pavel Izikson, Elyakim Kassel, and Mike E. Adel "A comparison of methods for in-chip overlay control at the 65-nm node", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.534510
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