Influence of line-edge roughness on MOSFET devices with sub-50-nm gates

Kiyoshi Shibata; Naoki Izumi; Kouichirou Tsujita

doi:10.1117/12.534508

24 May 2004 Influence of line-edge roughness on MOSFET devices with sub-50-nm gates

Kiyoshi Shibata, Naoki Izumi, Kouichirou Tsujita

Proceedings Volume 5375, Metrology, Inspection, and Process Control for Microlithography XVIII; (2004) https://doi.org/10.1117/12.534508
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

Line edge roughness (LER) poses a serious problem for the performance of MOSFET devices. In this work, we experimentally investigated the influence of LER on MOSFET devices. The conditions giving LERs were prepared with four kinds of photoresists, namely, a KrF resist and three ArF resists. We applied seven post-applied-baking (PAB)/post-exposure-baking (PEB) conditions for one of the ArF resists used in this work. We not only measured critical dimension (CD) and LER but also analyzed LER spectra with a commercially available CD SEM. As a result, we obtained the important knowledge that LER became larger as CD became finer and the trend became more marked for the transistors with larger LER. We experimentally found that LER of 9 nm at the gate length (L_g) of 50 nm increased off-state leakage (I_off) of MOSFET, and the fluctuation of threshold voltage (V_th). Finally, we verified that LER of less than 7 nm at L_g of 50 nm is required to prevent the increase of I_off, and that in the case of L_g of 70 nm, the fluctuation of V_th did not increase even if LER was as much as 7.5 nm.

Citation Download Citation

Kiyoshi Shibata, Naoki Izumi, and Kouichirou Tsujita "Influence of line-edge roughness on MOSFET devices with sub-50-nm gates", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.534508

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