Overlay errors induced by metallic stress: mechanism and solutions

Yulin Yen; Charles Chang; Francis Lin; Jason Su; Tahone Yang

doi:10.1117/12.533931

24 May 2004 Overlay errors induced by metallic stress: mechanism and solutions

Yulin Yen, Charles Chang, Francis Lin, Jason Su, Tahone Yang

Proceedings Volume 5375, Metrology, Inspection, and Process Control for Microlithography XVIII; (2004) https://doi.org/10.1117/12.533931
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

With an ever-increasing demand of stringent overlay control as a result of aggressive device scaling, lithographers are facing more challenges to maintain the inter-layer pattern registration accuracy. One of the critical factors is related to the integrity of monitor patterns (keys) when wafers undergo various process steps. It was reported that mis-reading of overlay registration could be induced by asymmetric film deposition on monitor keys. Lithographers go after more and more accurate controls on overlay performance as the overlay budget being constantly squeezed in face of ever increasing device density. Therefore, Fidelity between electric devices and registration inspection monitor key becomes one of concerned factors. Lots of papers addressed observations of overlay mis-reading induced by asymmetric film deposition on monitor key. In this report, both new mechanisms and new solutions are revealed. The mechanism of metal film stress induced scaling errors was identified. Besides, different kinds of metallic film configurations were conducted and shown to reduce previous scaling errors dramatically. Furthermore, a variety of new overlay keys without film-stress dependency were designed to overcome this issue. Both approaches reduced the mis-reading from tremendous to slight shift. This mis-alignment deviation is expected to be more severe during the migration from 200nm wafer to 300nm wafer as a result of a larger distance from wafer center to wafer edge. Those characterizations addressed in this report provide helpful information to the understanding of the overlay shift mechanism as well as solutions for better control.

Citation Download Citation

Yulin Yen, Charles Chang, Francis Lin, Jason Su, and Tahone Yang "Overlay errors induced by metallic stress: mechanism and solutions", Proc. SPIE 5375, Metrology, Inspection, and Process Control for Microlithography XVIII, (24 May 2004); https://doi.org/10.1117/12.533931

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KEYWORDS

Metals

Semiconducting wafers

Etching

Overlay metrology

Scanning electron microscopy

Inspection

Control systems

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