157-nm chromeless phase lithography for 45-nm SRAM gate

Toshifumi Suganaga; Kunio Watanabe; Seiji Matsuura; Takuya Hagiwara; Takamitsu Furukawa; Toshiro Itani; Kiyoshi Fujii

doi:10.1117/12.534897

28 May 2004 157-nm chromeless phase lithography for 45-nm SRAM gate

Toshifumi Suganaga, Kunio Watanabe, Seiji Matsuura, Takuya Hagiwara, Takamitsu Furukawa, Toshiro Itani, Kiyoshi Fujii

Proceedings Volume 5377, Optical Microlithography XVII; (2004) https://doi.org/10.1117/12.534897
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

157-nm lithography processes together with optimization of mask feature size and illumination conditions and chromeless mask (CLM) of mesa-type were used to fabricate a 45-nm gate by combining a high numerical aperture (NA) lens with off-axis illumination (OAI) and using Si-containing resist. It was observed that the minimum pitch for forming a 45-nm line was 140-nm. It was also shown that quadrupole illumination was the optimum OAI condition and the optimum mask feature size for forming a 45-nm line of 200-nm pitch was between 50 nm to 55 nm. In these conditions the normalized image log-slope value was about 3.0. It was demonstrated that a 45-nm SRAM gate with a depth of focus of 150 nm could be fabricated by combining these resolution enhancement techniques with high NA lithography and Si-containing resist. Furthermore the 45-nm SRAM-gate pattern was successfully transferred with a bi-layer process. From these results it was proven that fabrication of 45-nm node device could be achieved by using CLM with high NA lithography.

Citation Download Citation

Toshifumi Suganaga, Kunio Watanabe, Seiji Matsuura, Takuya Hagiwara, Takamitsu Furukawa, Toshiro Itani, and Kiyoshi Fujii "157-nm chromeless phase lithography for 45-nm SRAM gate", Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); https://doi.org/10.1117/12.534897

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