Fulfillment of model-based OPC for contact patterns in 60-nm level logic device

Sang-Wook Kim; Sung-Woo Lee; Chang-Min Park; Soo-Han Choi; Young-Mi Lee; Yool Kang; Gi-Sung Yeo; Jung-Hyeon Lee; Han-Ku Cho; Woo-Sung Han

doi:10.1117/12.536268

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28 May 2004 Fulfillment of model-based OPC for contact patterns in 60-nm level logic device

Sang-Wook Kim, Sung-Woo Lee, Chang-Min Park, Soo-Han Choi, Young-Mi Lee, Yool Kang, Gi-Sung Yeo, Jung-Hyeon Lee, Han-Ku Cho, Woo-Sung Han

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Proceedings Volume 5377, Optical Microlithography XVII; (2004) https://doi.org/10.1117/12.536268
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

Dummy contact generation procedure to apply off-axis illumination (OAI) to a contact layer in a 60 nm node device is described. The model based optical proximity correction (OPC) is also adopted to control the on-chip variation (OCV). The dummy contact size of 110 nm with the space distance of 90 nm between the main and dummy contact is used. By applying OPCed contact, the proximity variation is reduced less than 11 nm from 49 nm. The modeling methods are assessed by comparing delta edge placement error (EPE) values, which represent the model accuracy. The VTR_E model is shown to well correct the proximity variation, and it is adopted in our experiment. Applying to the arbitrary patterns of logic device and to generate more dummy patterns, the rule needs to be modified. The modified rule includes the dummy merge method, and the dummy contacts are automatically generated for the contact layer of 60 nm node logic device.

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Sang-Wook Kim, Sung-Woo Lee, Chang-Min Park, Soo-Han Choi, Young-Mi Lee, Yool Kang, Gi-Sung Yeo, Jung-Hyeon Lee, Han-Ku Cho, and Woo-Sung Han "Fulfillment of model-based OPC for contact patterns in 60-nm level logic device", Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004); https://doi.org/10.1117/12.536268

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