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28 May 2004 RET integration of CPL technology for random logic
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As IC fabrication processes are maturing for the 130nm node, IC devices manufacturers are focusing on 90nm device manufacturing at ever-lower k1 values. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at a similar k1 of near 0.3 using ArF. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique vs. the two masks and double exposure technique required for alternating phase shift masks (altPSM). The high mask cost of altPSM also discourages its use for low volume manufacturing. The two leading candidates candidates for 90nm node using KrF are: 6% attenuated PSM and CPL Technology. In this work, we present a methodology on how to use transmission tuning to achieve the best process latitude for patterning poly gate layer. First, we analyze the diffraction patterns from 6% attPSM and CPL mask features and identify the optimum transmission for various pitches. Next we describe how CPL mask can be used as a variable transmission attenuated mask to produce the best through pitch imaging performance and show a practical implementation method for applying to real device designs. Then we demonstrate how to integrate the optimized transmission tuning into the data process and OPC flow for generating CPL mask. Finally, we provide an example experimental result on a real device pattern.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stephen D. Hsu, Douglas J. Van Den Broeke, J. Fung Chen, Xuelong Shi, Michael Hsu, Thomas L. Laidig, Will Conley, Lloyd C. Litt, and Wei Wu "RET integration of CPL technology for random logic", Proc. SPIE 5377, Optical Microlithography XVII, (28 May 2004);


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