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3 May 2004 Feature level test patterns for characterizing residual process effects
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Layout test patterns are being pursued that are more sensitive than circuit patterns in detecting and quantifying residual processing effects. These patterns permit the rapid searching of layouts for the locations of worst-case process impacts, and may facilitate layout compensation at OPC speeds. These patterns have been taped-out along with snippets of circuits in preparation for experimental verification of the ability to link residual process effects to electronic design. The collection includes pattern-and-probe-based targets for measuring aberrations, illumination non-uniformity and etch-depth errors in phase-shifting masks, plasma etching with loading effects related to area and perimeter factors, and patterns for CMP orientation and feature proximity. The goal is to use these test patterns to develop maximum lateral impact functions for each individual process effect for use in fast-CAD techniques capable of inspecting large layouts.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Andrew R. Neureuther, Gregory R. McIntyre, Frank E. Gennari, Michael Lam, Jason P. Cain, Garth C. Robins, Edward Huang, Jihong Choi, Ling Wang, Lei Yuan, and Hideaki Oshima "Feature level test patterns for characterizing residual process effects", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004);


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