Paper
3 May 2004 Manufacturability of the X Architecture at the 90-nm technology node
Michael C. Smayling, Robin C. Sarma, Toshiyuki Nagata, Narain Arora, Michael P. Duane, Shiany Oemardani, Santosh Shah
Author Affiliations +
Abstract
In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael C. Smayling, Robin C. Sarma, Toshiyuki Nagata, Narain Arora, Michael P. Duane, Shiany Oemardani, and Santosh Shah "Manufacturability of the X Architecture at the 90-nm technology node", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); https://doi.org/10.1117/12.536027
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KEYWORDS
Optical proximity correction

Resistance

Manufacturing

Resistors

Semiconducting wafers

Metals

Lithography

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