Patterning sub-50-nm Fin-FET using KrF lithography tool

Navab Singh; S. Jagar; Sohan Singh Mehta; Moitreyee Mukherjee Roy; Rakesh Kumar; N. Balasubramanian

doi:10.1117/12.536040

3 May 2004 Patterning sub-50-nm Fin-FET using KrF lithography tool

Navab Singh, S. Jagar, Sohan Singh Mehta, Moitreyee Mukherjee Roy, Rakesh Kumar, N. Balasubramanian

Proceedings Volume 5379, Design and Process Integration for Microelectronic Manufacturing II; (2004) https://doi.org/10.1117/12.536040
Event: Microlithography 2004, 2004, Santa Clara, California, United States

Abstract

A method to fabricate a very thin channel body Fin-FET and Tri-gate MOSFET is presented. 8% Attenuated Phase-shift mask (APSM) and single phase chrome-less mask (CLM) techniques are evaluated to pattern fins in sub-50 nm regime using KrF lithography scanner with a maximum numerical aperture of 0.68. Some of the issues of single phase CLM technique with respect to fin patterning are highlighted. Dual Exposure With Shift (DEWS)’ is introduced to pattern gate lines down to 80 nm using binary mask.

Citation Download Citation

Navab Singh, S. Jagar, Sohan Singh Mehta, Moitreyee Mukherjee Roy, Rakesh Kumar, and N. Balasubramanian "Patterning sub-50-nm Fin-FET using KrF lithography tool", Proc. SPIE 5379, Design and Process Integration for Microelectronic Manufacturing II, (3 May 2004); https://doi.org/10.1117/12.536040

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available