Translator Disclaimer
28 May 2004 FET on ultrathin SOI (fabrication and research)
Author Affiliations +
Proceedings Volume 5401, Micro- and Nanoelectronics 2003; (2004)
Event: Micro- and Nanoelectronics 2003, 2003, Zvenigorod, Russian Federation
Some problems arisen from the fabrication of the nano-scale transistors are discussed: modification of the silicon-on-insulator (SOI) under (a) thinning procedure (multiplied oxidation), (b) structuring of the silicon nanolayers. Two types of SOI field effect transistors (FETs) were realized: in-plane-gate FET (IPGFET) with 40 nm minimum channel size and multi-channel top-gate FET on silicon on-insulator. The multi-channel 3D-gate FET fabricated on the uniform doped silicon layers are found to be the most advantageous variant of design.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Olga V. Naumova, Irina V. Antonova, Vladimir P. Popov, Yury V. Nastaushev, Tatiana A. Gavrilova, Marina M. Kachanova, Litvin V. Litvin, and Alexander L. Aseev "FET on ultrathin SOI (fabrication and research)", Proc. SPIE 5401, Micro- and Nanoelectronics 2003, (28 May 2004);

Back to Top