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8 September 2004 Parallel optical interconnects with mixed-signal OEIC and fibre arrays for high-speed communication
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We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8'8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.
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Dietmar Fey, Lutz Hoppe, Andreas Loos, Michael Fortsch, and Horst Zimmermann "Parallel optical interconnects with mixed-signal OEIC and fibre arrays for high-speed communication", Proc. SPIE 5453, Micro-Optics, VCSELs, and Photonic Interconnects, (8 September 2004);

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