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4 November 2004 Design and development of high-speed fiber-optic transmit and receive network for commercial and military applications
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Abstract
High Speed Multi-Channel Fiber-Optic Transmitter (Tx) and Receiver (Rx) modules are needed for communication Applications. The fiber optic network should take advantage of the high speeds (10 Gbps/channel) and have the ability to connect multiple systems using fiber-optic network capable of working with 100’s of Gigabits of information. In addition, the network should provide redundant links between nodes so that in case one node goes out of service, the remainder of the network remains operational. In this paper we will present design, development and performance results for 1x12 Tx and Rx module operating at 10Gbps/channel. Each of the 1x12 modules is capable of providing 120 Gbps/Module operations for Military and Commercial Applications. Experimental results on 1x12 channel modules will include performance characteristics at 10 Gbps and will demonstrate high performance fiber-optical Tx and Rx Modules. We will also present architecture and simulation for a Fiber-Optic Network Card that has the capability to transmit and receive data, add and drop data at each node, and provide dual network redundancy. This network card includes Tx, Rx modules, serializer and de-serializer (SERDES) and a cross bar switch. This architecture can be used as a building block for high-speed local area network applications and also applicable to optical backplanes for distributed microprocessor communication.
© (2004) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ashok K. Sood, Sriraj K. Bhadra, Paul R. Smith, Yash R. Puri, Mitchell Cross, Jason Ueda, Rakesh Patel, Jiang Liu, Wayne H. Chang, George J. Simonis, David V. Plant, Andrew G. Kirk, and Joshua D. Schwartz "Design and development of high-speed fiber-optic transmit and receive network for commercial and military applications", Proc. SPIE 5556, Photonic Devices and Algorithms for Computing VI, (4 November 2004); https://doi.org/10.1117/12.560671
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