Device analysis: a way to reduce patterning cost at mask and wafer level?

Artur P. Balasinski; Frank A.J.M. Driessen

doi:10.1117/12.569904

6 December 2004 Device analysis: a way to reduce patterning cost at mask and wafer level?

Artur P. Balasinski, Frank A.J.M. Driessen

Author Affiliations +

Proceedings Volume 5567, 24th Annual BACUS Symposium on Photomask Technology; (2004) https://doi.org/10.1117/12.569904
Event: Photomask Technology, 2004, Monterey, California, United States

Abstract

Preserving the accuracy of pattern reproduction on silicon with the decreasing linewidth usually requires paying increasingly higher prices for the masks. However, the advances in optical, device and circuit simulation tools are offering interesting alternatives to the tightening of reticle specifications. The performance of the next generation circuits can be verified by integrated simulation at the mask, device, and cell level. The tradeoff between mask quality, process options, product characteristics, and manufacturing cost can be thereby analyzed. Such integrated simulation impacts also mask shop and process deliverables. As an example, it was shown the potential to reduce reticle rejection rate by several times. In this work, integrated simulation helped choose the most economical option for the poly mask process, to control channel CD variation related to the discontinuity of gate pattern in multi-transistor memory cells. We evaluated the tradeoff between cell performance and the cost of the phase shift mask set to reduce poly CD variation. Based on the cell stability dependence on photo process parameters, we proved that the low cost approach can still yield economically satisfactory results.

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Artur P. Balasinski and Frank A.J.M. Driessen "Device analysis: a way to reduce patterning cost at mask and wafer level?", Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); https://doi.org/10.1117/12.569904

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