Full-chip manufacturing reliability check and correction (MRC2): a first step toward design for manufacturability with low k1 lithography

Michael Hsu; Tom Laidig; Kurt E. Wampler; Stephen Hsu; Xuelong Shi; J. Fung Chen; Douglas Van Den Broeke

doi:10.1117/12.568670

6 December 2004 Full-chip manufacturing reliability check and correction (MRC²): a first step toward design for manufacturability with low k₁ lithography

Michael Hsu, Tom Laidig, Kurt E. Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, Douglas Van Den Broeke

Author Affiliations +

Proceedings Volume 5567, 24th Annual BACUS Symposium on Photomask Technology; (2004) https://doi.org/10.1117/12.568670
Event: Photomask Technology, 2004, Monterey, California, United States

Abstract

Low k1 lithography process enables the production of 90nm and 65nm nodes by introducing advanced resolution enhancement technology (RET) mask with complex layout. To ensure the printed wafer outcome that meets the original IC design specifications, we need to consider the manufacturability and to verify it during design stage. This means that we need to characterize the process capabilities and use them as the input parameters to examine the upcoming design via simulation verification before mask making. For those of potentially weak or marginal layout design areas identified during the checking stage, we need to build a robust algorithm to improve the RET mask treatment process or to modify the design layout when necessary. This is the basic concept for Manufacturing Reliability Check & Correction (MRC2). In our implementation, MRC2 carries the wafer manufacturability information. By performing MRC2 during the design phase, we can better achieve the goal of Design for Manufacturing (DFM). In this paper, we present two example cases for a production worthy MRC2 - CPL (with two mask writing steps) and DDL (with two exposure masks). From our viewpoints, the first checking step needs to single out the "weak printing spots" or to map out the treated CPL/DDL features with unacceptable DOF and marginal exposure latitude. This allows using corrective actions to ensure a well-behaved printing of the entire chip during manufacturing. We recommend applying both MRC2 and electrical verification in the design verification loop iteratively until circuit performance prediction becomes satisfactory. The looping process generates useful feedback that adds to the RET knowledge database; hence, a more efficient DFM procedure.

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Michael Hsu, Tom Laidig, Kurt E. Wampler, Stephen Hsu, Xuelong Shi, J. Fung Chen, and Douglas Van Den Broeke "Full-chip manufacturing reliability check and correction (MRC²): a first step toward design for manufacturability with low k₁ lithography", Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); https://doi.org/10.1117/12.568670

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KEYWORDS

Photomasks

Manufacturing

Critical dimension metrology

Printing

Resolution enhancement technologies

Computer aided design

Lithography

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