Integrating RET and mask manufacturability in designs for local interconnect for sub-100-nm trenches

Nishrin Kachwala; Travis E. Brist; Rick S. Farnbach

doi:10.1117/12.569848

6 December 2004 Integrating RET and mask manufacturability in designs for local interconnect for sub-100-nm trenches

Nishrin Kachwala, Travis E. Brist, Rick S. Farnbach

Proceedings Volume 5567, 24th Annual BACUS Symposium on Photomask Technology; (2004) https://doi.org/10.1117/12.569848
Event: Photomask Technology, 2004, Monterey, California, United States

Abstract

Model based OPC for low k1 lithography has a large impact on mask cost, and hence must be optimized with respect to mask manufacturability and mask cost without sacrificing device performance. Design IP blocks not designed with the lithography process in mind (not "litho friendly") require more complex RET/OPC solutions, which can in turn result in unnecessary increases in the mask cost and turn around time. These blocks are typically replicated many times across a design and can therefore have a compounding effect. Design for manufacturing (DFM) techniques verify and alleviate complex interactions between design and process. DFM can be applied at various stages in your design-to-silicon flow. We will discuss how these DFM methods are applied and implemented at Cypress. We will also show how design rules are defined and present several methods for injecting OPC/RET awareness into the designs prior to mask manufacture.

Citation Download Citation

Nishrin Kachwala, Travis E. Brist, and Rick S. Farnbach "Integrating RET and mask manufacturability in designs for local interconnect for sub-100-nm trenches", Proc. SPIE 5567, 24th Annual BACUS Symposium on Photomask Technology, (6 December 2004); https://doi.org/10.1117/12.569848

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