Sampling plan optimization for CD control in low k1 lithography

Masafumi Asano; Toru Koike; Toru Mikami; Hideaki Abe; Takahiro Ikeda; Satoshi Tanaka; Shoji Mimotogi

doi:10.1117/12.600370

10 May 2005 Sampling plan optimization for CD control in low k₁ lithography

Masafumi Asano, Toru Koike, Toru Mikami, Hideaki Abe, Takahiro Ikeda, Satoshi Tanaka, Shoji Mimotogi

Proceedings Volume 5752, Metrology, Inspection, and Process Control for Microlithography XIX; (2005) https://doi.org/10.1117/12.600370
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

For advanced process control, a sampling plan for critical dimension measurement is optimized through empirical considerations concerning the nature of error and a statistical approach. The metric of the optimization is the accuracy of lot mean estimation. In this work, critical dimension errors are classified into static and dynamic components. The static component is defined as the error which repeats through lots while keeping its tendency, and the dynamic as the error whose tendency changes by lot. In the basic concept of our sampling plan, sampling positions and size are determined from the static and dynamic error, respectively. The balance of sampling number of wafer, field and pattern is obtained under the restriction of total sampling size by a statistical theory with some assumptions. Based on the concept, we could make a sampling plan for 65 nm CMOS lithography.

Citation Download Citation

Masafumi Asano, Toru Koike, Toru Mikami, Hideaki Abe, Takahiro Ikeda, Satoshi Tanaka, and Shoji Mimotogi "Sampling plan optimization for CD control in low k₁ lithography", Proc. SPIE 5752, Metrology, Inspection, and Process Control for Microlithography XIX, (10 May 2005); https://doi.org/10.1117/12.600370

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