Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination

Patrick K. Montgomery; Richard Peters; Cesar Garza Sr.; Jonathan Cobb; Bill Darlington; Colita Parker; Stan Filipiak; Danny Babbitt

doi:10.1117/12.600785

12 May 2004 Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination

Patrick K. Montgomery, Richard Peters, Cesar Garza Sr., Jonathan Cobb, Bill Darlington, Colita Parker, Stan Filipiak, Danny Babbitt

Author Affiliations +

Proceedings Volume 5753, Advances in Resist Technology and Processing XXII; (2004) https://doi.org/10.1117/12.600785
Event: Microlithography 2005, 2005, San Jose, California, United States

Abstract

Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm. In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lithography process. As resist trim etch becomes more aggressive over time, LER on etched gates becomes less linked to the roughness in resist, and more to a product of the coupled lithography and etch processes. The aspect ratio of trimmed resist features increases and patterns become susceptible to pattern collapse, bending and tearing. Conversely if aspect ratios are maintained through the trim process, then the ability of the resist to protect the substrate from the final etch is degraded as the resist thickness decreases. A novel method of resist fluorination is presented that significantly reduces LER and pattern deformations such as collapse, tearing and bending. Experimental data shows that resist fluorination can make possible sub-30 nm etched polysilicon gates at aspect ratios on the order of 5:1. The same fluorination process yields LER improvements of 15% to 20% on average with largest improvements in the mid-range roughness frequencies of 10 - 50 μm^-1. The length scale, or inverse of frequency, is also used in the study. The resist fluorination process is described as it is used in the study. Experimental and analytical data show how the process is reduced to practice and how LER and pattern deformation are improved. The fluorination process is simple to integrate into a standard wafer flow, has low cost of ownership, and yields large process improvements.

Citation Download Citation

Patrick K. Montgomery, Richard Peters, Cesar Garza Sr., Jonathan Cobb, Bill Darlington, Colita Parker, Stan Filipiak, and Danny Babbitt "Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination", Proc. SPIE 5753, Advances in Resist Technology and Processing XXII, (12 May 2004); https://doi.org/10.1117/12.600785

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available